A prior art device is shown in FIG. 1a. With no charge on floating gate 114F, this device is normally in its low threshold state (V.sub.T =+1.0 V). It may be programmed to a high threshold state (V.sub.T +5 V) by applying a high voltage V.sub.D to the drain 120D and control gate 114C (V.sub.D is typically 15 V and V.sub.C is typically 20-25 V with the source voltage V.sub.S =OV, and the substrate bias volage V.sub.B =OV). The shifting of the threshold voltage is accomplished through hot electron injection at the drain pinchoff region of the channel, as shown schematically by the arrows beneath floating gate 114F in FIG. 1A. The injected electrons are permanently trapped on the polysilicon floating gate 114F which is isolated from the substrate and control gate by dielectric films 126C and 126F. Film 126F is usually 1000.degree. A of thermal oxide. The presence of excess electrons on the floating gate 1114F requires V.sub.C to go to a more positive voltage to reach the inversion (or "threshold") voltage. A cell written into its high threshold state will not conduct when V.sub.C is +5 V during the read cycle. All devices in the memory array can be erased by illuminating the array with ultraviolet light. This light provides the trapped electrons sufficient energy to escape out of the floating polysilicon into the SiO2 layers above or below it, to be collected in the substrate or by the floating gate (this is known as internal photoemission). Alternatively the array can be erased by applying a strong electric field between the floating gate and the control gate or substrate, resulting in momentary electronic conduction through the respective SiO2 film (this is known as Fowler--Nordheim conduction).
Three key factors control the efficiency of selective writing in a memory array utilizing the device of FIG. 1A. First is the strength of capacitive coupling between the floating gate and control gate (Cc1 in FIG. 1B). This depends on the geometric overlap between the two gates and on the thickness and refractive index of the insulating film 126C between the two. Unfortunately, if this film is made too thin, there is the possibility of shorts between the two gates, particularly during the high voltage condition existing during "write." The second and third factors are the channel length L between source and drain, and the channel doping concentration P. The shorter L and the higher P, the more efficient is the hot electron injection mechanism. However, a short L can cause punchthrough between source 120S and drain 120D when the drain is in the high voltage condition, and a high doping P can cause junction avalanche breakdown, also during the high voltage condition. Both phenomena must be avoided absolutely in a memory array.
The prior art has also taught implicitly or explicitly that the parasitic capacitances from control gate 114C and floating gate 114F to source 120S and drain 120D adversely affect the operation of cell 110, and must be minimized by critical self alignment techniques. Especially to be minimized is side capacitance Cd1 between floating gate 114F and drain 120D which allow floating gate 114F to follow the potential on drain 120D. During write, because of the high value of V.sub.D, every unaddressed cell on the selected column exhibits low level conduction (about 10 microamps) due to Cd1 coupling of the drain to the floating gates of non-accessed cells thereby turning on slightly certain of these cells. A 64K EPROM (256 rows by 256 columns) has a worst case parasitic current due to this effect of several milli-amps, an amount above the write current of the addressed cell (1 milliamp). Currents of this magnitude may load the data line voltage and cause errors due to reduced write efficiency. This condition is known as "drain-turn-on."